Techie Foulders

 1.Design fsm for 10011, overlapping 2.Design fsm using 2bit grey code, one-hot code 3.Edge triggered D flipflop verilog 4.Level sensitive D verilog 5.Verilog code for generating 8bit even number 6.Verilog code for multiplication (*4) without using * operator 7.Design circuits using given waveforms 8.Draw the circuit for detecting multiples of 4 for a 32bit number

 UVM Questions What are some of the benefits of UVM methodology? What are some of the drawbacks of UVM methodology? Explain the concept of Transaction Level Modelling? What is the difference between an  uvm_object and  uvm_component  class? What are TLM ports and TLM Fifos? What is an analysis port and analysis fifo and  where are they used? Explain the  protocol handshake between  a sequencer and driver ? What is the difference  between a  sequence and sequence item? Is it possible to collect responses from DUT back to a sequence and if so how? What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM arbitration mechanism on sequencer? What is the difference between grab() and lock() on sequencer? What is the difference between a pipelined  and non-pipelined driver? What is the difference between early randomization and late randomization of sequences? Write a  sample  sequence code that  generates a stream...

 1.What is combinational Loop 2.Difference between Blocked RAM and Distributed RAM 3.What is setup and hold slack? 4.Tperiod =10ns,Tsetup=0.2ns,Thold=0.9ns, Calculate setupand hold slack 5.For 4KB memory, no of address lines? Starting address? Ending Address? 6.How many 2x1 mux are required to design 64x1 mux? 7.WAVP for n-bit carry adder using generate block 8.For 2-bit ring and Johnson counter no of used and unused states? 9.Design 2x1 mux using EX-OR gate? 10.Discuss about STA 11.Discuss about regions in Verilog 12.FPGA synthesis and implementation 13.What is STA and DDA 14.Limitation of STA 15. Timing Passes 16.Synchronous and asynchronus reset 17. What is sensitivity list 18.WAVP for multiple of 2 19.Explain about FIFO 20.Design 2X4 Decoder 21.FPGA design Flow 22.FPGA vs ASIC differences 23.FSM for sequence detection of 1011 24.WAVP for 2-FF synchronizer 25.Using EX_OR gate design buffer and inverter 26.WAVP for swapping two numbers 27. Application of FSM 28.Design FF for clk/...