General DV interview Questions

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 UVM Questions

  1. What are some of the benefits of UVM methodology?
  2. What are some of the drawbacks of UVM methodology?
  3. Explain the concept of Transaction Level Modelling?
  4. What is the difference between an  uvm_object and  uvm_component  class?
  5. What are TLM ports and TLM Fifos?
  6. What is an analysis port and analysis fifo and  where are they used?
  7. Explain the  protocol handshake between  a sequencer and driver ?
  8. What is the difference  between a  sequence and sequence item?
  9. Is it possible to collect responses from DUT back to a sequence and if so how?
  10. What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM arbitration mechanism on sequencer?
  11. What is the difference between grab() and lock() on sequencer?
  12. What is the difference between a pipelined  and non-pipelined driver?
  13. What is the difference between early randomization and late randomization of sequences?
  14. Write a  sample  sequence code that  generates a stream of ethernet packets?
  15. How can you specify weightage for a sequence when started on a sequencer?
  16. What is  the difference between a monitor and a scoreboard in UVM methodology?
  17. What is meant by  factory and what is its importance?
  18. What is the difference between creating an object using  new()  and create()?
  19. What are the difference  phases in UVM  and what is the order of their execution?
  20. What are objections and how are they useful?
  21. How can you implement a simulation timeout  mechanism using UVM methodology?
  22. What is meant by factory override  and what are different types of overriding possible with UVM factory?
  23. What is a virtual sequence and  where do we use a virtual sequence?  What are its benefits?
  24. What is  uvm_config_db  and what is it used for?
  25. Why should any  uvm component be registered with factory?
Digital Logic 

  1. What is the difference between Combinational and Sequential circuits?
  2. Simplify the following logic function f(ABC) using K-maps     f(A,B,C) =  ( A + B + C’) . (A + B’+ C’)
  3. What is the difference between “Ripple Carry Adder” and “Carry Look-ahead Generator”?
  4. What is  the concept of “Setup” and “Hold” time?
  5. How can you implement and/or/not gate using NAND/NOR?
  6. What is the difference between flip flop and latches?
  7. What is the difference between synchronous reset and asynchronous reset?
  8. What is meant by clock domain crossing?
  9. Design a state machine to detect a   stream of  “1011”  in a  serial input stream?
  10. How many flip flops are needed to implement a 32 bit register ?
  11. Explain the difference  between binary and gray encoding and the benefits of each?
  12. What is one hot encoding ?
  13. What is meant by race condition ?
  14. Design a circuit to  divide a clock  by  2 ? and  by 3 ?
  15. What is 1’s complement and 2’s complement?
  16. Which gates are called universal gates and why?
SV

  1. What is the difference between  bit and logic  data types?
  2. What is the difference between  logic[7:0] and byte  data type?
  3. What is the difference between  queues, dynamic arrays and associative arrays?
  4. What is the difference between a class and object?
  5. What is  inheritance  and multiple inheritance? Does SystemVerilog support multiple inheritance?
  6. What is a virtual function?
  7. What is the difference  between  a static  member of a class and non-static member of class?
  8. What is the difference between  overriding a method   vs   overloading a method?  Does SystemVerilog support both?
  9. What is meant by forward declaration of a class and when is it used?
  10. What is a “ref” and  “const  ref” argument  in SystemVerilog functions?
  11. Can  a static function  have an argument with “ref” keyword?
  12. What is the difference between pass by reference and pass by value ?
  13. What is the difference between  “==”  and  “===”  logical equality operators?
  14. Which of the logical equality operator  “==”  or “===” i s used by   case statements to detect condition match?
  15. What is the difference between   fork..join_none and  fork..join_any ?
  16. What is the  use of modports inside  clocking blocks?
  17. What is the difference between  pre and post increment operators –   ++a   vs  a++ ?
  18. What is a  bind  construct used for in SystemVerilog?
  19. What is the difference between  immediate and concurrent assertions?
  20. What is the difference  between overlapping and non-overlapping implication operators?
Coding

  1. What is the difference between a static variable, local variable and a global variable in any programming language?
  2. What do you mean by inline function?
  3. What is the difference between  heap and stack ?
  4. What is the difference between ++a  and  a++  in any programming language?
  5. What is meant by memory leak?
  6. What is the difference between struct and class ?
  7. What is the difference between class an object?
  8. What is polymorphism ?
  9. What is  inheritance and multi inheritance?
  10. What are public, private and protected data members?
  11. What is  function overriding  vs function overloading?
  12. What are static methods and where do we use it?
  13. What is an abstract class?
  14. What is a virtual function?
  15. Write a  C program to compute number of  ones in a bit vector?
  16. Write a C/SystemVerilog program to generate Fibonacci series?

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