Design Verification -Juntran Fresher 2021

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 1.What is combinational Loop

2.Difference between Blocked RAM and Distributed RAM

3.What is setup and hold slack?

4.Tperiod =10ns,Tsetup=0.2ns,Thold=0.9ns, Calculate setupand hold slack

5.For 4KB memory, no of address lines? Starting address? Ending Address?

6.How many 2x1 mux are required to design 64x1 mux?

7.WAVP for n-bit carry adder using generate block

8.For 2-bit ring and Johnson counter no of used and unused states?

9.Design 2x1 mux using EX-OR gate?

10.Discuss about STA

11.Discuss about regions in Verilog

12.FPGA synthesis and implementation

13.What is STA and DDA

14.Limitation of STA

15. Timing Passes

16.Synchronous and asynchronus reset

17. What is sensitivity list

18.WAVP for multiple of 2

19.Explain about FIFO

20.Design 2X4 Decoder

21.FPGA design Flow

22.FPGA vs ASIC differences

23.FSM for sequence detection of 1011

24.WAVP for 2-FF synchronizer

25.Using EX_OR gate design buffer and inverter

26.WAVP for swapping two numbers

27. Application of FSM

28.Design FF for clk/2 with 50% and 25% duty cycle

29.Differnce betwwen mealy and moore machine

30.LUT


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