Design Verification -Juntran Fresher 2021

-

 1.What is combinational Loop

2.Difference between Blocked RAM and Distributed RAM

3.What is setup and hold slack?

4.Tperiod =10ns,Tsetup=0.2ns,Thold=0.9ns, Calculate setupand hold slack

5.For 4KB memory, no of address lines? Starting address? Ending Address?

6.How many 2x1 mux are required to design 64x1 mux?

7.WAVP for n-bit carry adder using generate block

8.For 2-bit ring and Johnson counter no of used and unused states?

9.Design 2x1 mux using EX-OR gate?

10.Discuss about STA

11.Discuss about regions in Verilog

12.FPGA synthesis and implementation

13.What is STA and DDA

14.Limitation of STA

15. Timing Passes

16.Synchronous and asynchronus reset

17. What is sensitivity list

18.WAVP for multiple of 2

19.Explain about FIFO

20.Design 2X4 Decoder

21.FPGA design Flow

22.FPGA vs ASIC differences

23.FSM for sequence detection of 1011

24.WAVP for 2-FF synchronizer

25.Using EX_OR gate design buffer and inverter

26.WAVP for swapping two numbers

27. Application of FSM

28.Design FF for clk/2 with 50% and 25% duty cycle

29.Differnce betwwen mealy and moore machine

30.LUT


Comments

Post a Comment

Popular posts from this blog

Qualcomm Interview (DFT Role)- Fresher

-
There were in total 5 rounds (4 technical rounds + 1 HR round) First round: 1. What do I understand by DFT and the need for DFT? 2. What are scan flip flops? 3. What are the different simulation techniques for testing? What do you infer from transient delay simulation? 4. A circuit with several and-or gates was given, need to identify the input test vector for detecting a slow-to-rise fault at a particular net. 5. What is BIST?  5b. What are the different techniques used for compaction?  6. What is boundary-scan standard? (JTAG) 7. How do you rank various sorting algorithms? (insertion, bubble, etc) 8. What do you understand from hazards in a processor design? How did you overcome control hazards? 9. What happens in a deep pipelined system? (Performance related, flushing all stages of the pipeline when branch prediction fails. Increased latency). 10. Write a Verilog code for a RAM, let the address space be a parameter. 11. Are you familiar with writing scripts in- bash, PERL, ...
Read more

AMD Interview questions - Physical Design

-
(1st round -- 45 minutes)**  1) Introduce myself.  2) Operation of MOSFET.  3)Types of MOSFET.  4) What is the difference between BJT, MOSFET and CMOS.  5) Why CMOS. 6) Why cmos for low power applications.  7) Basics questions on current equation of MOSFET.  8) basic questions on layers of MOSFET.  9) What is threshold voltage.  10) some questions on equation of threshold voltage.  11) PVT parameters.  12) what is the secondary effects.  13) Voltage divider rule.  14) series circuit operation.  15) parallel circuit operation.  16) oscillator operation.  17) universal gates.  18) Realization of XOR and XNOR using NAND and NOR gates.  19) Which has highest area NAND or NOR and Why.  \20) ASIC vs SOC. (2nd round --- 45 minutes )*   1) Introduce myself.  2) Complete PD flow.  3) inputs to the PD tool.  4) Some commands on Innovus tool.  5) what are the end cap cells w...
Read more

Cerium systems fresher recruitment Interview Questions [1hr]

-
1) What is FPGA ? 2) What is difference between ASIC and FPGA ? 3) Can we replace FPGA with ASIC ? 4) What FPGA consists of actually ? 5) Tell the flow of FPGA like how we will implement a code on FPGA ? 6) What are Universal gates?  Implemented NOR gate using Nand gate? Is Mux Universal gate ? If yes implement And & Or gates using 2:1 mux ? 7) Basic diff between Latch & FF ? 8) Make a D latch using 2:1 Mux ? 9) Implement the ckt for 101 pattern detecting don't use the FSM but implement in sequential ? 10) Draw the CMOS gate for 2-input Nand & 2-input Nor gates ? 11) What are synthesizable and unsynthesizable constructs in Verilog? which one will be used when ? 12) Write verilog code for up-down counter? 14) Why Nand gate is preferable over Nor gate ? 15) Draw 3-bit Ring and Johnson Counter along with their States ?
Read more