Techie Foulders

1. In which technology nodes you have worked for and completed the tape out? 2. What are the values of ‘X’ and ‘Y’ coordinates of your block? 3. How is your block design shape and how the macros are placed in that shape, why you preferred that design style? 4. By using which toolbox in the GUI window or in encounter shell you completed your placement for your block? 5. How many pins are there in the design and the spacing between the pins you provided? 6. Spacing between the macros formula? 7. On which basis you will place the macros on if the design constraints are fixed to do?   8. What are the issues you face if the design is like the above one and how will solve that? 9. What is the pitch of power and metals which you have considered? 10.W hat is the formula for power stripes? 11. What are global net connections and what is the command u use in the encounter? 12. What does the global net connections file contain exactly? 13. How you provided Power rings and Power stripes to your de

1. Floorplan guidelines? 2. Well tap cells at on/off domain? 3. What is an endcap cell? Where will you place? What happens if don’t place it? 4. Setup time and hold time 5. Channel length calculation and soft blockage and hard blockage? 6. What is congestion? Where did you see congestion in your block? 7. DRV fixing techniques? 8. Cloning algorithm? 9. Suppose if our block has Clock Tran, data Tran, set up, hold, noise violations from these violations fixing order in ECO stage? 10. Power plan for on-off domains? 11. What is power switches working? 12. What is the difference between HVT, LVT, and SVT cells? 13. Can we place HVT and LVT side by side? (if a cell have 4X the size we can place) 14. What are the reasons for via not placing? How do you place via? 15. Suppose two different nets have 100 u length and 1u width and 2u width, how is delay between the two nets, and what is the dominating factor? 16.What is site?

1.Difference between  latch and FF 2. Setup and hold time definition 3.How to fix setup and hold time 4.ASIC FLOW explanation 5.Difference between the asynchronous and synchronous counter and Design procedure 6.Difference between synchronous and asynchronous reset. 7.Active low rst and active high rst and in the industry which is preferred and why 8.Difference between processor and controller 9.Example for synchronous and asynchronous reset using D FF 10.How to convert D-FF to T-FF procedure

There were in total 5 rounds (4 technical rounds + 1 HR round) First round: 1. What do I understand by DFT and the need for DFT? 2. What are scan flip flops? 3. What are the different simulation techniques for testing? What do you infer from transient delay simulation? 4. A circuit with several and-or gates was given, need to identify the input test vector for detecting a slow-to-rise fault at a particular net. 5. What is BIST?  5b. What are the different techniques used for compaction?  6. What is boundary-scan standard? (JTAG) 7. How do you rank various sorting algorithms? (insertion, bubble, etc) 8. What do you understand from hazards in a processor design? How did you overcome control hazards? 9. What happens in a deep pipelined system? (Performance related, flushing all stages of the pipeline when branch prediction fails. Increased latency). 10. Write a Verilog code for a RAM, let the address space be a parameter. 11. Are you familiar with writing scripts in- bash, PERL, etc?  Sec

1. Latch-up in CMOS (using diagram..explain) 2. SR FF using NAND gates 3. What are universal gates 4. Difference between latch and FF 5. About a project I did  6. VLSI design flow. 7. What is LVS 8. What is Async reset sync reset 9.How to swap 2 variable without using swapping the 3rd variable 10. What is Fifo? 11. Project, sta, memory, interrupts, project, iot, wifi communication, dma, combn seqn, blocking non blocking,  delay, sta basics, scaling 12. Power optimization process in sta, how to do timing analysis, what do you need for that, and many more 13.Vlsi design flow 14. Wheatstone bridge 15.Dual flop synchroniser 16.Electrostatic integrity effects 17. Why finfet 18. Some digital also like counter design. Setup, hold, its mitigation, some definitions of sta related things 19. Edge detecting circuit 20.  What is setup time and hold time, transistor parameters, diagram of setup and hold.timing violations 

DIGITAL DESIGN  https://www.youtube.com/watch?v=M0mx8S05v60&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm – Digital Electonics by Neso Academy.  http://www.fullchipdesign.com/ https://www.youtube.com/watch?v=Y8FvvzcocT4&list=PL1221EE053D86FDA1 – Digital Design by NPTEL.  https://www.youtube.com/watch?v=nzxT84jTbGk&list=PLPIqCiMhcdO7bBmieyG5u41x2Ogcn67Bs – Digital Design Course.  https://www.electronicshub.org/binary-adder-and-subtractor/ -- Electronics Hub. https://www.electronicshub.org/priority-encoder/#Simple4-Input_Priority_Encoder VHDL  http://home.deib.polimi.it/sami/VHDL_merged.pdf -- VHDL Merged https://www.scribd.com/document/278006745/VHDL-merged-pdf -- VHDL Merged http://www.dejazzer.com/ee478/lecture_notes/lec08_packages.pdf -- VHDL Package and Other Construts.  https://www.youtube.com/watch?v=0Ho4rDswOeE&list=PL0pU5hg9yniZ2ka-XBXROXNR0pAEAEFCB --Intel FPGA Official Youtube Link(Verilog,VHDL,Timing,Quartus Prime Software,Qsys Editor,Platform Deisgner etc).  https:

  https://drive.google.com/file/d/1iZuXmcQHFGUKRVQr_Fb-j0r90EihT8z3/view?usp=sharing

Synopsys Campus Interview 2021 Questions Tell me about u r self. Round 1: 1)Difference between latch and ff. 2) write a Verilog code for the right shift and left shift depends on sel input. 3)D latch Verilog code. 4) normal dff  verilogcode 5)DFF working  6) difference between ASIC and FPGA 7) using dff(if en is there (dout =din) or if en is no there  it holds the previous value) 8) In DFF use only if the latch is infer r not  Round 2: ( 30 minutes ) 1. What is verification and why do we use UVM. 2. Explain the first concept that I understood in UVM. 3. What is FSM 4. Design an FSM for traffic light controllers. 5. Design an FSM for sequence 1011. 6. Difference between Mealy and Moore in terms of the structure of sequence 1011. 7. What are user-defined data types in C. 8. Tell the output of the code snippet. int arr[ ] = {1,11,21,31,51 }; int *p = &arr; Print("%d", *p++); Print("%d", *p); Print("%d", *++p); Print("%d", *p); Print("%d&quo

AMD 2021 CAMPUS Interview Questions  1st round  1) Differences between MOSFET and FINFET ? 2) Puzzle:- A blind man walking in a desert has 2 red pills and 2 blue pills with him. He has to take one red pill and one blue pill each per day. How can he do that correctly 3) Limitations of MOSFET 4) Puzzle :- If a man climbs 15 m well . He climbs 4 m everyday and slips 3 m . How many days it takes for him to get outside of the well ? 5) What is set up time and hold time 6) What is set up time and hold time violations 7) What is metastability and do you know its physical significance 8) What is a critical path 9) How can you improve the timing 10) How can you fix the set up time violations 11) Implement a 2:1 mux for AND gate 12) Draw the timing diagram of half adder 13) What is blocking and non blocking assignments 14) What is synchronous and Asynchronous reset 15) Why do we need DFT and what do you mean by that? 16) Explain briefly the methods of DFT 17) Why do you need to make flip flops i