Techie Foulders

1. DIFF between NLDM, CCS AND ECSM 2. WHY AND WHAT TYPE OF CONTEXT GDS IS USED FOR CHARACTERIZATION. 3. CHAR SPECIFICATIONS AND HOW IT IS GENERATED 4. HOW INDEX VALUES WERE CALCULATED IN LIBERTIES 5. MILLER CAPACITANCE 6. METHODOLOGY FOR CALCULATING SETUP/HOLD 7. USAGE OF SPECIAL CELLS AND ITS IMPORTANCE AND WHAT ALL THE EXTRA FACTORS THAT NEED TO BE TAKEN CARE WHILE CHARACTERIZING THESE AND WHAT EXTRA ATTRIBUTES WILL SPECIFY THE BEHAVIOUR OF THESE CELLS ( POWER GATERS, ISOLATION, LEVEL SHIFTERS, RETENTIONS, MULTI BIT FLOPS, SYNCRONIZERS) 8. WHY APACHE ?? WHY BOT LIBERTY POWER MODELS 9. METHODOLOGY HOW APACHE POWER CALCULATION IS DIFFERENT FROM LIBERTY POWER CALCULATION. 10. USAGE OF APACHE MODELS AT TOP LEVEL 11. VALIDATION CHECKS FOR LIBERTIES 12. CCS NOISE CALCULATION. 13. HOW THRESHOLD POINTS WERE FIXED  14. IMPACT OF NEGATIVE DELAY AND ITS SOURCE 15. IS SETUP/HOLD IS ALWAYS POSITIVE ?? IF NOT WHY ? 16. WHY SETUP+HOLD SHOULD ALWAYS BE GREATER THAN 0 <script data-ad-client="...

1. What are the Inputs to start floorplan 2. Explain the Complete PNR Flow 3. What are the check in PD Flow  4. What are Setup and hold definitions 5. How are Tlu/tlu+ files generated from Drc and lvs. What are they? 6.What are base drcs and how it is fixed? 7.How is Power planning done  8.What are Sdc constraints like false paths, multicycle paths 9.What is Timing closure, how is the experiments done without swapping, skewing, sizing 

  Why matching? Types of Matching? How do we decide which matching for specific device? To overcome error due to Process variation, Ion Implantation…. To minimize variation in x & y axis we go for Cross Coupled Common Centroid, Interdigitized, Common Centroid based on our requirements. Diff pair we go for Cross coupled Common Centroid .->> For Amplifier it is Voltage dependent, by controlling Vgs we can control its ON & OFF operation and hence current. Hence Voltage places a crucial role than Current for Current Mirror->> hence matching of Differential Amplifier is very very important. On what factors we consider whether to go for matching or not. As there are additional disadvantages of Matching. Speed->>Parasitic cap will be added. We need to minimize cap Why we always shield to Ground and not VDD? There are more variation in VDD as there may be two voltages 3.3V or 1.8V but little variation in ground because of n...

  What are the Blocks Present in an Amplifier? Differential Amplifier Current Mirror Current Sink Resistor & Capacitors. What are the Factors considered while Matching Amplifier? Routing is equidistant Dummy Variation is minimized both x & Y axis What are the Factors considered while Floor Planning from Scratch? Important->>Input and Output taken where signals come so that they don’t cross over each other Guard rings->> latch UP Signal flow Matching Why do we put guard rings around devices? To prevent latch up. To reduce resistance (make less chance of ON transistor) Prevention to overcome Latch Up? Use guard rings->> to reduce resistance. SOI What happens if more Current occurs during latch up? Creates destruction of device & short Which signal will you shield clock/biasing? Clock more switching takes place so we go for shielding biasing. Explain Antenna effect. If we have violation in M...

 I am a VLSI professional, working towards helping entry level professionals in their job hunt. The students are not industry ready and need some guidance to take interviews. So this blog is focusing on fresher candidates aspiring to enter electronics - vlsi Industry.  Whatsapp Group link: https://chat.whatsapp.com/H5J7WxjnyH60inHqLyas9h

 1.Realize 10k Ω Resistor using unit Resistance of 3k Ω using any number of Series/ Parallel Resistors? 2.Realize 1.5pF Capacitor using unit Capacitance of 1pF using any number of Series/ Parallel Capacitor? 3) 4) 5) 6 7. Conversion of Micro to Milli- 1uv= mV 8. Conversion of Milli to Micro - 1.25mv= uV 9. Conversion of Pico farad to Femto Farad- 0.2pF= fF 10. Calculate Resistance Given Sheet Resistance = 10 Ω /square, W= 15um, L=1.5um, t=10nm 11. Draw Cross-Section of NMOS Interview Questions 1. What is MOS?? Why do we use Poly instead of Metal? 2. Why the body is highly Doped ?? ( For example in NMOS we use P+ why can’t we use only P- or just P type) 3. If there is no Variation in VDD or GROUND Is there is a chance for Latch Up? 4. What care do you take to Prevent Latch-Up? 5. What is the Concept of D...

1) Difference Between Latch and FlipFlop 2) Difference Between Synchronous and Asynchronous Reset 3) Draw a flip flop using latches? After it is done what will be the clock of FF (positive or negative edge) ? 4) Draw a frequency divide by 2 ckt not using T FF but using D FF? 5) What are fsm and its advantages? 6) 10110 Sequence detect using mealy with 2- bit overlapping ? After it is done they asked me to implement this particular FSM using hardware ? 7) write a code for 3:1 mux in verilog using ternary operator (? :) 8) what is difference between wire and reg? what are default values of wire and reg and why? 9) what is synthesis and what is simulation ? 10) Different abstraction levels in verilog? 11) Write a code in verilog where if l = 0 it should work as upcounter and if l = 1 than the counter should take input from outside (i;e Data_in) so whatever the data_in value from there again it should start counting ?

Project Academic (mini project, main project) I choose VLSI digital  So he ask me the questions from that 1. How CMOS is constructed 2. Why pmos up n nmos down 3. Power dissipation 4. How to reduce it 5. Transmission logic 6.Then he ask me to write a VHDL code of FSM on notepad

  Explain the flow of physical design and inputs and outputs for each step in flow What parameters (or aspects) differentiate Chip Design and Block level design? How do you place macros in a full chip design? Differentiate between a Hierarchical Design and flat design? Which is more complicated when u have a 48 MHz and 500 MHz clock design? How will you decide the die size? What are the input needs for your design (for synthesis stage & Physical Design stage)? What is SDC constraint file contains? What is Aspect Ratio and core utilization factor? Why higher metal layers are preferred for Vdd and Vss? What is the significance of negative slack? What is meant by abutment? Where do we use it? Define the following terms  (i) Leaf cell  (ii) Composite cell

  STEP 1: Load the 4 main Inputs   i.e. Netlist [Gate level Netlist] Lef   [ Technology Lef, Macro Lef, Stdcell Lef] Libs   [Logical libraries or timing libraries] SDCs [ Design Constraints] Lef contains : No of metal layers, Direction of metal layer H/V, Resistance and capacitance per unit square, width spacing and pitch of all metal layers, area, thickness, Via information [double cut and single cut] a subset of DRC rules. Macro Lef : All macro information ex dimensions and coordinates, macro pin information. Std cell Lef : All physical dimensions of the std cells and input pin a b and out, their geometry. Libs: NLDM’s         All timing information of the standard cells ex nand, and, or flip-flop.         Like cell delay information for that much input transition and that much output load. timing sense i.e. Positive or negative unate. Setup and hold constraints of the sequential circuits . For that much data transitio...