5G TestBed Round 1 Interview Questions

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1) Difference Between Latch and FlipFlop

2) Difference Between Synchronous and Asynchronous Reset

3) Draw a flip flop using latches? After it is done what will be the clock of FF (positive or negative edge) ?

4) Draw a frequency divide by 2 ckt not using T FF but using D FF?

5) What are fsm and its advantages?

6) 10110 Sequence detect using mealy with 2- bit overlapping ? After it is done they asked me to implement this particular FSM using hardware ?

7) write a code for 3:1 mux in verilog using ternary operator (? :)

8) what is difference between wire and reg? what are default values of wire and reg and why?

9) what is synthesis and what is simulation ?

10) Different abstraction levels in verilog?

11) Write a code in verilog where if l = 0 it should work as upcounter and if l = 1 than the counter should take input from outside (i;e Data_in) so whatever the data_in value from there again it should start counting ?

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