Capgemini - Analog Layout Interview

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 What are the Blocks Present in an Amplifier?

  • Differential Amplifier

  • Current Mirror

  • Current Sink

  • Resistor & Capacitors.

What are the Factors considered while Matching Amplifier?

  • Routing is equidistant

  • Dummy

  • Variation is minimized both x & Y axis

What are the Factors considered while Floor Planning from Scratch?

  • Important->>Input and Output taken where signals come so that they don’t cross over each other

  • Guard rings->> latch UP

  • Signal flow

  • Matching

Why do we put guard rings around devices?

To prevent latch up. To reduce resistance (make less chance of ON transistor)

Prevention to overcome Latch Up?

Use guard rings->> to reduce resistance.

SOI

What happens if more Current occurs during latch up?

Creates destruction of device & short

Which signal will you shield clock/biasing?

Clock more switching takes place so we go for shielding biasing.

Explain Antenna effect. If we have violation in Metal4 how do we solve.

  • If there is violation in Metal4 we have to use essentially Metal5 and not Metal3.

  • Top metal has low resistance compared to bottom one so we use top metal which will result in less IR drop.

  • During fabrication lower level metals are fabricated first then higher level metals

  • We have violation in Metal4 and we need to go for Metal5 to avoid violation. But if we use Metal3 then again charge accumulation of Metal3 will get added to Metal4 so we should only go for higher Metals that is Metal5

What is the necessity to go for Density checks? Why density check max is also required ( What happens if more M1 Is filled?

If minimum is not present then because of etching, no planarization hence possibility of Opens if we don’t follow minimum density rules.

What is the difference observed while going from higher technology nodes to lower?

  • Parasitic cap is more

  • More cross coupling

  • IR drop is less->> We need to carefully plan Floor Plan.

Why don’t we go for Common centroid Matching for Current Mirror, even Current mirror is very important in providing multipliers. Only differential Amplifier we go for Common Centroid.

  • For Amplifier it is Voltage dependent, by controlling Vgs we can control its ON & OFF operation and hence current.

  • Hence Voltage places a crucial role than Current for Current Mirror->> hence matching of Differential Amplifier is very very important.

Why don’t we follow Coaxial shielding in lower technology/finfet?

We follow Coaxial shielding only in higher nodes. As in lower nodes all are tightly packed. And we follow strictly even metals horizontal orientation & odd vertical. By following advanced rules we cannot do coaxial shielding for lower nodes.

What does Temperature Sensor Block do? What does it do?

What are the Blocks in LDO? IS it only a regulator?

What are blocks in PLL? Anything as Buffer?,

  • Biasing

  • Delay stages

  • Output stages

Clock routing is very critical. We need to make equidistant routing to match resistor A->>B->>C so that all are same.

What is HVDRC? Why do we go for that?

BGR? Which is more important matching BGR/Resistor

  • BGR (Has BJT, Opamp, Resistor laddering)

How do we Implement layout of BGR 1:8? How do we connect parallel so that length is maintained constant?

We place 1 in centre and remaining in 3*3 pattern & use thick metal to short all Collector together. Likewise Base & Emitter.

One of the terminal goes to Resistor End.

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