Techie Foulders

 1.Design fsm for 10011, overlapping 2.Design fsm using 2bit grey code, one-hot code 3.Edge triggered D flipflop verilog 4.Level sensitive D verilog 5.Verilog code for generating 8bit even number 6.Verilog code for multiplication (*4) without using * operator 7.Design circuits using given waveforms 8.Draw the circuit for detecting multiples of 4 for a 32bit number

 UVM Questions What are some of the benefits of UVM methodology? What are some of the drawbacks of UVM methodology? Explain the concept of Transaction Level Modelling? What is the difference between an  uvm_object and  uvm_component  class? What are TLM ports and TLM Fifos? What is an analysis port and analysis fifo and  where are they used? Explain the  protocol handshake between  a sequencer and driver ? What is the difference  between a  sequence and sequence item? Is it possible to collect responses from DUT back to a sequence and if so how? What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM arbitration mechanism on sequencer? What is the difference between grab() and lock() on sequencer? What is the difference between a pipelined  and non-pipelined driver? What is the difference between early randomization and late randomization of sequences? Write a  sample  sequence code that  generates a stream of ethernet packets? How can you specify weightage for a sequen

 1.What is combinational Loop 2.Difference between Blocked RAM and Distributed RAM 3.What is setup and hold slack? 4.Tperiod =10ns,Tsetup=0.2ns,Thold=0.9ns, Calculate setupand hold slack 5.For 4KB memory, no of address lines? Starting address? Ending Address? 6.How many 2x1 mux are required to design 64x1 mux? 7.WAVP for n-bit carry adder using generate block 8.For 2-bit ring and Johnson counter no of used and unused states? 9.Design 2x1 mux using EX-OR gate? 10.Discuss about STA 11.Discuss about regions in Verilog 12.FPGA synthesis and implementation 13.What is STA and DDA 14.Limitation of STA 15. Timing Passes 16.Synchronous and asynchronus reset 17. What is sensitivity list 18.WAVP for multiple of 2 19.Explain about FIFO 20.Design 2X4 Decoder 21.FPGA design Flow 22.FPGA vs ASIC differences 23.FSM for sequence detection of 1011 24.WAVP for 2-FF synchronizer 25.Using EX_OR gate design buffer and inverter 26.WAVP for swapping two numbers 27. Application of FSM 28.Design FF for clk/2 wi

1.       Round 1       1. Problems on Equivalent Resistance 2 Operation of CMOS Inverter 3. Problems on Transient, Steady state Analysis 4. Problems on calculating Equivalent Resistance in Op-Amp circuits 5. What is loading effect? 6. Operation of Inverter with R in place of pmos & NMOS , disadvantage in connecting in that way? 7. Latch and Flip-flop difference 8. What is test Engineer Job Role. 9. Problems on Expected Clock period to overcome Setup violation 10. Ideal characteristics of Op-Amp.   ROUND 2(45min) 1.  W hat it diode, operation of diode   2. what is transistor, what happens if voltage is increased ?   3. Avalanche Breakdown 4. Applications of diode 5. Identify Essential Prime Implicants (EPI), Prime Implicants in given problems 7. Can Flip flop be built with Latch ?   8. Can Latch be built with clock? 9. What is kelvin Connection ? 10. Uses of Buffer ? 11. Draw Inverting, non-Inverting Integrator, Differentiator using op-amp & output Voltage formulas for t

(1st round -- 45 minutes)**  1) Introduce myself.  2) Operation of MOSFET.  3)Types of MOSFET.  4) What is the difference between BJT, MOSFET and CMOS.  5) Why CMOS. 6) Why cmos for low power applications.  7) Basics questions on current equation of MOSFET.  8) basic questions on layers of MOSFET.  9) What is threshold voltage.  10) some questions on equation of threshold voltage.  11) PVT parameters.  12) what is the secondary effects.  13) Voltage divider rule.  14) series circuit operation.  15) parallel circuit operation.  16) oscillator operation.  17) universal gates.  18) Realization of XOR and XNOR using NAND and NOR gates.  19) Which has highest area NAND or NOR and Why.  \20) ASIC vs SOC. (2nd round --- 45 minutes )*   1) Introduce myself.  2) Complete PD flow.  3) inputs to the PD tool.  4) Some commands on Innovus tool.  5) what are the end cap cells why its used in placement.  6) what is congestion.  7) Disadvantages of Congestion.  8) How do you transfer clock signal from

Q1: 1. PCB design flow explain? Design Flow Process 1. DESIGN REVIEW 2. COMPONENT DATA SHEETS 3. MECHANICAL DATA IMPLEMENT 4. LIBRARY MANAGEMENT 5. CONTRAINT SETTING 6. PART PLACEMENT 7. POWER & SPLIT PLANES 8. ROUTING CRITICAL NET 9. SIGNAL INTEGRITY 10. ROUTE REMAINDER OF NON-CRITICAL ROUTES 11. FINAL DRC CHECKS  12. SILKSCREEN & ASSEMBLY 13. FAB LAYER UPDATION 14. FINAL CAM OUTPUT Q2 : What is EMI/EMC? where does these exits & how to control them? Answers: EMI: It is the process which gives out disruptive EM waves, transmits energy from one electronic device to another via radiated/conducted paths. In common usage, the term refers to RF signals. EMC: The capability of electrical/electronic systems/equipment & devices to operate in their intended EM environment within a defined margin of safety & at design levels/performance, without suffering or causing unacceptable degradation as a result of EMI. Where does exits: Any source of changing voltage anywhere in the c