PCB Layout Questions
Q1: 1. PCB design flow explain?
Design Flow Process
1. DESIGN REVIEW
2. COMPONENT DATA SHEETS
3. MECHANICAL DATA IMPLEMENT
4. LIBRARY MANAGEMENT
5. CONTRAINT SETTING
6. PART PLACEMENT
7. POWER & SPLIT PLANES
8. ROUTING CRITICAL NET
9. SIGNAL INTEGRITY
10. ROUTE REMAINDER OF NON-CRITICAL ROUTES
11. FINAL DRC CHECKS
12. SILKSCREEN & ASSEMBLY
13. FAB LAYER UPDATION
14. FINAL CAM OUTPUT
Q2 : What is EMI/EMC? where does these exits & how to control them?
Answers:
EMI: It is the process which gives out disruptive EM waves, transmits energy from one electronic device to another via radiated/conducted paths. In common usage, the term refers to RF signals.
EMC: The capability of electrical/electronic systems/equipment & devices to operate in their intended
EM environment within a defined margin of safety & at design levels/performance, without suffering or
causing unacceptable degradation as a result of EMI.
Where does exits:
Any source of changing voltage anywhere in the circuit will generate emissions. The greater the voltage or current amplitude within the circuit, the greater the source of emissions. The faster that a voltage
changes level, the greater the potential interference.
PCB Design Tips:
• Avoid slit apertures in PCB layout, particularly in GND planes or near current paths.
• Areas of high impedance give rise to high EMI, so use wide tracks for power lines on the trace sides.
• Make signal tracks stripline & include GND plane & PWR plane whenever possible.
• Keep HF/RF tracks as short as possible & layout the High Frequency tracks first.
• On sensitive components & terminations, use guard ring & Ground fill wherever possible.
• A guard ring around trace layers reduces emission out of the board; also, connect to Ground only at a single point and make no other use of the guard ring.
• If possible, make tracks run orthogonally between adjacent layers.
• Don’t loop tracks, even between layers, as this forms a receiving or radiating antenna
• Don’t leave floating conductor areas, as they act as EMI radiators; if possible connect to GND plane
COMPONENTS FOR EMI REDUCTION & EMC
1. Inductors
2. Capacitors
3. Transformers
4. Ferrite Beads
Answers:
EMI: It is the process which gives out disruptive EM waves, transmits energy from one electronic device to another via radiated/conducted paths. In common usage, the term refers to RF signals.
EMC: The capability of electrical/electronic systems/equipment & devices to operate in their intended
EM environment within a defined margin of safety & at design levels/performance, without suffering or
causing unacceptable degradation as a result of EMI.
Where does exits:
Any source of changing voltage anywhere in the circuit will generate emissions. The greater the voltage or current amplitude within the circuit, the greater the source of emissions. The faster that a voltage
changes level, the greater the potential interference.
PCB Design Tips:
• Avoid slit apertures in PCB layout, particularly in GND planes or near current paths.
• Areas of high impedance give rise to high EMI, so use wide tracks for power lines on the trace sides.
• Make signal tracks stripline & include GND plane & PWR plane whenever possible.
• Keep HF/RF tracks as short as possible & layout the High Frequency tracks first.
• On sensitive components & terminations, use guard ring & Ground fill wherever possible.
• A guard ring around trace layers reduces emission out of the board; also, connect to Ground only at a single point and make no other use of the guard ring.
• If possible, make tracks run orthogonally between adjacent layers.
• Don’t loop tracks, even between layers, as this forms a receiving or radiating antenna
• Don’t leave floating conductor areas, as they act as EMI radiators; if possible connect to GND plane
COMPONENTS FOR EMI REDUCTION & EMC
1. Inductors
2. Capacitors
3. Transformers
4. Ferrite Beads
Ans: Signal Integrity is the ability of a signal to generate correct responses in a circuit. A signal with good signal integrity has digital levels at required voltage levels at required times.
Ringing: Imbalances in impedances generally cause undesirable effects in a circuit. When the reflection coefficients of the source & the load are of opposite polarity, the reflections alternate in polarity. The signal oscillates, or "rings," about its final, steady-state value. You can reduce the ringing by making the electrical line length short compared with the rise & fall times of the waveform. You can also cut ringing by providing better matching of the source & load impedances to that of the transmission line.
Undershoot is the second peak or valley past the settling voltage - the deepest valley for a rising edge & the highest peak for a falling edge. Excessive undershoot can cause false clocking or data errors
(glitches).
Overshoot is the first peak or valley past the settling voltage - the highest voltage for a rising edge & the lowest voltage for a falling edge. Undershoot is the next valley or peak. Excessive overshoot can
cause protection diodes to turn on, leading to early field failures.
Q4: What is cross talk & how to reduce the cross talk?
Ans: Crosstalk refers to unintended EM coupling between traces, wires, trace-to-wire, cable assemblies, components, & other electrical components subject to EM field disturbance. Crosstalk depends on the length of the parallel traces, the space between them & the rise & fall time of the signal.
Some of the crosstalk occurrences are
· Crosstalk between wires, cables & traces affects intersystem performance.
· Crosstalk is considered a functionality concern (signal quality).
· Design techniques to prevent crosstalk.
First, note the following observations:
* Decreasing the trace separation increases the mutual capacitance Cm & the crosstalk.
* With parallel traces, longer parallel lengths increase the mutual inductance Lm & the crosstalk.
* Decreasing the rise time of the signal, increases the cross-talk.
Some of the measures to be taken to reduce crosstalk are:
1. Minimize physical distance between components during placement.
2. Minimize parallel routed trace lengths.
3. Group logic families according to functionality. Keep bus structure tightly controlled.
4. Provide proper termination on impedance-controlled traces, or traces rich in RF harmonic energy.
5. Locate components away from Input/output interconnects & other areas susceptible to data corruption & coupling.
6. Reduce trace impedance and signal drive level.
7. Reduce signal-to-ground reference distance separation.
8. Route adjacent layers (microstrip/stripline) orthogonal. This prevents capacitive coupling between adjacent layers
9. Avoid routing of traces parallel to each other. Provide sufficient separation between traces to minimize inductive coupling(the 3 W Rule: )
10. Partition or isolate high noise emitters (clock, I/O, high-speed interconnects, etc.) onto Different layers within the Stackup assignment.
11. Route signal on adjacent layers perpendicular to each other wherever possible. (especially keep analog and digital signals are routed together).
12. Keep the clock lines away from the I/O signals lines or have a good clock shielding to prevent coupling.
13. Keep spacing between the adjacent active traces greater than trace width.
14. Keep clock & other HF signals grouped together & separated from connectors, other low speed & sensitive traces such as interrupt or reset lines.
15. Use narrow traces (8 mils or less) to increase HF dumping & reduce capacitive coupling.
Ans: Crosstalk refers to unintended EM coupling between traces, wires, trace-to-wire, cable assemblies, components, & other electrical components subject to EM field disturbance. Crosstalk depends on the length of the parallel traces, the space between them & the rise & fall time of the signal.
Some of the crosstalk occurrences are
· Crosstalk between wires, cables & traces affects intersystem performance.
· Crosstalk is considered a functionality concern (signal quality).
· Design techniques to prevent crosstalk.
First, note the following observations:
* Decreasing the trace separation increases the mutual capacitance Cm & the crosstalk.
* With parallel traces, longer parallel lengths increase the mutual inductance Lm & the crosstalk.
* Decreasing the rise time of the signal, increases the cross-talk.
Some of the measures to be taken to reduce crosstalk are:
1. Minimize physical distance between components during placement.
2. Minimize parallel routed trace lengths.
3. Group logic families according to functionality. Keep bus structure tightly controlled.
4. Provide proper termination on impedance-controlled traces, or traces rich in RF harmonic energy.
5. Locate components away from Input/output interconnects & other areas susceptible to data corruption & coupling.
6. Reduce trace impedance and signal drive level.
7. Reduce signal-to-ground reference distance separation.
8. Route adjacent layers (microstrip/stripline) orthogonal. This prevents capacitive coupling between adjacent layers
9. Avoid routing of traces parallel to each other. Provide sufficient separation between traces to minimize inductive coupling(the 3 W Rule: )
10. Partition or isolate high noise emitters (clock, I/O, high-speed interconnects, etc.) onto Different layers within the Stackup assignment.
11. Route signal on adjacent layers perpendicular to each other wherever possible. (especially keep analog and digital signals are routed together).
12. Keep the clock lines away from the I/O signals lines or have a good clock shielding to prevent coupling.
13. Keep spacing between the adjacent active traces greater than trace width.
14. Keep clock & other HF signals grouped together & separated from connectors, other low speed & sensitive traces such as interrupt or reset lines.
15. Use narrow traces (8 mils or less) to increase HF dumping & reduce capacitive coupling.
Q5 : Write some general guidelines for component placement?
Ans : Component placement can influence the amount of EMI generated. The guidelines below are general approaches to minimize EMI.
• Keep leads on TH components short. Mount the components as close to the PCB as possible and trim
leads if necessary.
• Place all components associated with one clk trace closely together. This reduces the trace length & reduces radiation.
• Place high-current devices as closely as possible to the power sources.
• Minimize the use of sockets in HF portions of the board. Sockets introduce higher inductance & mismatched impedance.
• Keep crystal, oscillators, & clk generators away from I/O ports & board edges. EMI from these devices can be coupled onto the I/O ports.
• Position crystals so that they lie flat against the PC board. This minimizes the distance to the GND plane & provides better coupling of EM fields to the board.
• Connect the crystal retaining straps to the GND plane. These straps, if ungrounded, can behave as an antenna and radiate.
• Provide a GND pad equal/larger than footprint under crystals & osc on the component side of the board. This GND pad should be tied to the GND planes with multiple vias.
Microstrip or stripline routing are ways to route signals on a PCB.
Microstrip has the signal line on an outer layer.
Microstrip refers to a trace routed on an outside layer of the PCB separated by a dielectric from the reference plane (GND/VCC).
This technique allows easy access to the signal line.
Stripline routing refers to a trace routed on an inside layer with 2 reference Planes.
Stripline has the signal line sand-wiched between 2 power planes.
This Technique theoretically offers the cleanest signals, because the signal line is shielded on both the sides. There is no easy access to the signal lines.
Dual Stripline has the two signal layers sand-wiched between 2 power planes.
Technique theoretically offers the not cleanest signals, because the signal line are parallel to each other.
To avoid cross talk or any Parallel routing need to route it orthogonally . There is no easy access to the signal lines.
Ans : Component placement can influence the amount of EMI generated. The guidelines below are general approaches to minimize EMI.
• Keep leads on TH components short. Mount the components as close to the PCB as possible and trim
leads if necessary.
• Place all components associated with one clk trace closely together. This reduces the trace length & reduces radiation.
• Place high-current devices as closely as possible to the power sources.
• Minimize the use of sockets in HF portions of the board. Sockets introduce higher inductance & mismatched impedance.
• Keep crystal, oscillators, & clk generators away from I/O ports & board edges. EMI from these devices can be coupled onto the I/O ports.
• Position crystals so that they lie flat against the PC board. This minimizes the distance to the GND plane & provides better coupling of EM fields to the board.
• Connect the crystal retaining straps to the GND plane. These straps, if ungrounded, can behave as an antenna and radiate.
• Provide a GND pad equal/larger than footprint under crystals & osc on the component side of the board. This GND pad should be tied to the GND planes with multiple vias.
Q6 : What is microstripline and stripline Routing?
Ans :Microstrip or stripline routing are ways to route signals on a PCB.
Microstrip has the signal line on an outer layer.
Microstrip refers to a trace routed on an outside layer of the PCB separated by a dielectric from the reference plane (GND/VCC).
This technique allows easy access to the signal line.
Stripline routing refers to a trace routed on an inside layer with 2 reference Planes.
Stripline has the signal line sand-wiched between 2 power planes.
This Technique theoretically offers the cleanest signals, because the signal line is shielded on both the sides. There is no easy access to the signal lines.
Dual Stripline has the two signal layers sand-wiched between 2 power planes.
Technique theoretically offers the not cleanest signals, because the signal line are parallel to each other.
To avoid cross talk or any Parallel routing need to route it orthogonally . There is no easy access to the signal lines.
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