Techie Foulders

-
Hi guys, this is Vishnu from Techie Foulders. Our initiative is to make you my friends get latest updates of technology 

Comments

Post a Comment

Popular posts from this blog

Qualcomm Interview (DFT Role)- Fresher

-
There were in total 5 rounds (4 technical rounds + 1 HR round) First round: 1. What do I understand by DFT and the need for DFT? 2. What are scan flip flops? 3. What are the different simulation techniques for testing? What do you infer from transient delay simulation? 4. A circuit with several and-or gates was given, need to identify the input test vector for detecting a slow-to-rise fault at a particular net. 5. What is BIST?  5b. What are the different techniques used for compaction?  6. What is boundary-scan standard? (JTAG) 7. How do you rank various sorting algorithms? (insertion, bubble, etc) 8. What do you understand from hazards in a processor design? How did you overcome control hazards? 9. What happens in a deep pipelined system? (Performance related, flushing all stages of the pipeline when branch prediction fails. Increased latency). 10. Write a Verilog code for a RAM, let the address space be a parameter. 11. Are you familiar with writing scripts in- bash, PERL, ...
Read more

AMD Interview questions - Physical Design

-
(1st round -- 45 minutes)**  1) Introduce myself.  2) Operation of MOSFET.  3)Types of MOSFET.  4) What is the difference between BJT, MOSFET and CMOS.  5) Why CMOS. 6) Why cmos for low power applications.  7) Basics questions on current equation of MOSFET.  8) basic questions on layers of MOSFET.  9) What is threshold voltage.  10) some questions on equation of threshold voltage.  11) PVT parameters.  12) what is the secondary effects.  13) Voltage divider rule.  14) series circuit operation.  15) parallel circuit operation.  16) oscillator operation.  17) universal gates.  18) Realization of XOR and XNOR using NAND and NOR gates.  19) Which has highest area NAND or NOR and Why.  \20) ASIC vs SOC. (2nd round --- 45 minutes )*   1) Introduce myself.  2) Complete PD flow.  3) inputs to the PD tool.  4) Some commands on Innovus tool.  5) what are the end cap cells w...
Read more

Capgemini - Analog Layout Interview

-
  What are the Blocks Present in an Amplifier? Differential Amplifier Current Mirror Current Sink Resistor & Capacitors. What are the Factors considered while Matching Amplifier? Routing is equidistant Dummy Variation is minimized both x & Y axis What are the Factors considered while Floor Planning from Scratch? Important->>Input and Output taken where signals come so that they don’t cross over each other Guard rings->> latch UP Signal flow Matching Why do we put guard rings around devices? To prevent latch up. To reduce resistance (make less chance of ON transistor) Prevention to overcome Latch Up? Use guard rings->> to reduce resistance. SOI What happens if more Current occurs during latch up? Creates destruction of device & short Which signal will you shield clock/biasing? Clock more switching takes place so we go for shielding biasing. Explain Antenna effect. If we have violation in M...
Read more