Qualcomm Interview (DFT Role)- Fresher

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There were in total 5 rounds (4 technical rounds + 1 HR round)

First round:

1. What do I understand by DFT and the need for DFT?

2. What are scan flip flops?

3. What are the different simulation techniques for testing? What do you infer from transient delay simulation?

4. A circuit with several and-or gates was given, need to identify the input test vector for detecting a slow-to-rise fault at a particular net.

5. What is BIST? 

5b. What are the different techniques used for compaction? 

6. What is boundary-scan standard? (JTAG)

7. How do you rank various sorting algorithms? (insertion, bubble, etc)

8. What do you understand from hazards in a processor design? How did you overcome control hazards?

9. What happens in a deep pipelined system? (Performance related, flushing all stages of the pipeline when branch prediction fails. Increased latency).

10. Write a Verilog code for a RAM, let the address space be a parameter.

11. Are you familiar with writing scripts in- bash, PERL, etc? 

Second Round:

1. How was the first round? What were you asked? 

2. What is the need of having multiprocessors? 

3. What is cache coherency?

4. Explain one protocol? MESI

5. What are isolation cells? For the given circuit how would you provide isolation? (Either OR or AND isolation)

6. What is set-up time? What is hold time? For the given circuit identify any violations

7. How would you overcome hold violations? What is negative hold time?

8. Two puzzles.

Third round:

1. How was your experience so far? He explained the work environment and how his made a career out of it.

2. Draw a CMOS inverter, explain the transfer characteristics.

3. Behaviour of transfer characteristics when PMOS drive strength is increased and NMOS drive strength is increased.

4. Interchange PMOS and NMOS, draw the transfer characteristics. 

5. Now, consider a dynamic CMOS NAND logic, what would happen when you impose a pattern of this on the circuit. 

6. Why did you draw a spike in the transient characteristics?

7. What is a direct mapped cache, explain for a particular block size which cache should you prefer? Direct, Set or Fully associative.

8. Why did you choose `timescale as this in your project?

9. Have you ever come across the term launch-off-capture? (I answered no)

10. What happens during metastability? Between tsu and thold which constraint should I always satisfy?

Fourth Round 4:

1. Tell me about yourself.

2. Let's start with basic questions why sync reset and why async. reset?

3. For the given circuit identify tsu and thold violations, if any.

4. What do you think is the Vdd is the latest technology nodes? (I said 0.7-0.8 V).

4b. What are various leakages present.

4c. What are short channel effects and what is subthreshold conduction?

5. Explain the dependency of mobility on temperature?

6. Puzzle 

7. Why do we need stuck at fault modeling?

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