Qualcomm Interview Questions -2021 Physical Design

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1. Floorplan guidelines?

2. Well tap cells at on/off domain?

3. What is an endcap cell? Where will you place? What happens if don’t place it?

4. Setup time and hold time

5. Channel length calculation and soft blockage and hard blockage?

6. What is congestion? Where did you see congestion in your block?

7. DRV fixing techniques?

8. Cloning algorithm?

9. Suppose if our block has Clock Tran, data Tran, set up, hold, noise violations from these violations fixing order in ECO stage?

10. Power plan for on-off domains?

11. What is power switches working?

12. What is the difference between HVT, LVT, and SVT cells?

13. Can we place HVT and LVT side by side? (if a cell have 4X the size we can place)

14. What are the reasons for via not placing? How do you place via?

15. Suppose two different nets have 100 u length and 1u width and 2u width, how is delay between the two nets, and what is the dominating factor?

16.What is site?

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