Physical Design -Qualcomm 2021

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1.In which technology nodes you have worked for and completed the tape out?
2.What are the values of ‘X’ and ‘Y’ coordinates of your block?
3.How is your block design shape and how the macros are placed in that shape, why you preferred that design style?
4.By using which toolbox in the GUI window or in encounter shell you completed your placement for your block?
5.How many pins are there in the design and the spacing between the pins you provided?
6.Spacing between the macros formula?
7.On which basis you will place the macros on if the design constraints are fixed to do? 
8.What are the issues you face if the design is like the above one and how will solve that?
9.What is the pitch of power and metals which you have considered?
10.What is the formula for power stripes?
11.What are global net connections and what is the command u use in the encounter?
12.What does the global net connections file contain exactly?
13.How you provided Power rings and Power stripes to your design and macros?
14.What are the metal layers considered for Vdd and Vss for macros?
15.What does the Technology lef file exactly contain?
16.Floorplan inputs and guidelines and encounter commands after importing the design and audit checks?
17.How you fix Drc and Drv’s after Power planning?

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