Cadence Analog Layout (3+ Experience)

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Interview Questions

1. Tell me about yourself?

2. Draw the Block Diagram/Circuit of LDO?         

3. What is Diode Connected/ Current Mirror?

4. Consideration of Floor Plan?

 

5. Drawback of Common Centroid Matching?

Ø  Two rows.

Ø  For lower technologies it can be harmful for the gates and generally not used. (channel length is less)

Ø  Larger set of gates is the routing that is required to connect them. (This could add capacitance)

Ø  Complex routing, more CAP, more area

 

7. How to minimize parasitic? What happens if Parasitic is present?

Ø  Time increases, Delay Increases

Ø  Keeping apart, Going for Higher Metals, Overlap Drain/Source, increase the spacing of all the nets from the net which is critical

Ø  Use higher metals for the net in which parasitic capacitance is important.

Ø  Increase the spacing of all the nets from the net which is critical (for which parasitic capacitance is important).

Ø  Put some other reference signal (with which parasitic capacitance is not so important) in between the nets for which lower parasitic capacitance required. This is shielding.

Ø  Avoid too much parallel routing of metals.

 

8. What is Electro migration? What is IR drop? Which is more critical?

      Current Handling Issue for Electro Migration

       Widen path- Resistance decreases

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