Techie Foulders

Round - 1 1. Self Introduction 2. Higher and lower nodes differences 3. WPE, STI, LOD 4. CMOS Latchup 5. Projects Explanation & it's Constraints Round - 2 1. EM & IR 2. Types of LVS Errors 3. Antenna Effect 4. Softchecks 5. ERC 6. Double Patterning Round-3 1. Network Analysis 2. How to prevent magnetic field coupling to the clock signals 3. Types of Shielding

Floor plan of the top level Working of block Signal flows Which all blocks worked in that Frequency of the block Vg and current of the block What are the challenges faced How fixed critical issues Have you done shielding They will give scenario and asking to calculate current and same they are asking to calculate width of metal fabrication steps MOSFETs operations inverter characteristics Diff CMOS and MOSFETs latch up matching types of that Differential amplifier Current mirror wpe antenna effect lod and sti em and IR crosstalk shielding ESD channel length modulation

Set- A  UVM pr jaarha tha mai bola nhi aata Task vs function Tell me about your Asic setup & hold time SV ka assertion Puzzle: There are three boxes, one contains only apples, one contains only oranges, and one contains both apples and oranges. The boxes have been incorrectly labeled such that no label identifies the actual contents of the box it labels. Opening just one box, and without looking in the box, you take out one piece of fruit. By  Fork join What is leakage and dynamic power Set-B (1)Current project (2)Setup time  (3)Hold time (4)Latch (5)Reg. (6)What is your interest  (7)Inversion layer (MOSFET) (8)Proportion delay (9)insertion delay (10)Fanout  (11)Coupling capacitor (12)Dynamic power (13)Leakage current (14)Threshold voltage (15)Cross talk (16)Are know about CMOS circuit (logic gate) /Synthesis/ ASIC/LVS Extraction?? Set-C Steps of physical design  Techniquefor reducing leakage and dynamic power Need of testing Difference between analog a...

Set-A  1. Can u quickly brief about your self for next 5 minutes? 2. How good u are in digital electronics? 3. Can u quickly built xnor gate with muxes? 4. How many 2:1 muxes require to built an xnor gate? 5. There is a triangle, each corner of the triangle have one object. That objects can move any direction  from the corners.What is the probability that any two objects collide each other? 6. What is SETUP and HOLD times? 7. How will u solve the SETUP violation? Set-B Difference between asic and fpga What are Trade of parameter in lpic? Area speed and power If setup or hold violates what will be output What is synthesis. Tool used for synthesis Set-C 1.which hdl languages do u know? 2.fibonacci series in verilog you reach a number that 16bit register cannot hold 3.a system which checks if 16bit input is a prime number and gives one bit output as 1 if it prime and 0 if it not prime 4.how approximate multipliers implemented in my project What was my approach? What was error? Ho...

Set-A  Project Hold  Setup Holdviolation  Brief project Intterupt Latch FF Design flow Pointer  Data type in c Null pointer Static variable Dynamic variable diff Mealy Moore application Which is faster Diff used  STA Sync reset  Async rese Set-B What is verilog A and verilog Ams Seriel protocols Thermometer coding Gray coding Set up and hold how to resolve  LRC circuit What is amplification Set-C How to fix IR drop without using straps How to fix setup violation without using buffer What is tie high and tie low  What is anteena effect How to make latch to flipflop Set-D Bjt  Differences between bjt and MOSFET Why mosfet whynot  bjt Diff amplifier concepts Opamp gains Verilog coding styles Some puzzles like aptitude Some microprocessor concepts  Set-E  Projects in details Implement verilog code for LCM of two 16 bit numbers Aptitude Q based on Speed time distance (two trains with different speed and starting with different delay...

 1.Pipelining 2.Performance improvement in a pipelined processor compared to a non pipelined processor.  3.Basics of System verilog and system verilog assertions -> Randomisation and constrained randomisation  4)Types of cache mapping -> Direct, k-way set associative and fully associative mapping, cache tagging  5)Need for instruction and data caches  6)Systolic arrays

 1. Explain matching techniques. (we need to take example) 2. why matching is done? 2. How to Place dummies? 3. Why dummies are not placed at the top and bottom sides? 4. explain sheilding. 5. what preventions you take for latch-up? 6. Explain antenna effect. How to overcome it? How reverse bias diode will discharge? What is the source for accumulated charges? 7. which type of sheilding you have done? 8. VCO considerations. 9. half cell technique. 10. why higher metal is preferred for VCO routing. 11. Explain PLL. What type of input is given for PLL. 12. explain LDO 13. antenna ratio calculations 14. electromigration 15. how placing jumper can prevent antenna effect? 16. What will you do when you are getting em after completion of layout. If you don’t have area to increase the metal width. 17. How delay stages are placed in VCO? 18. metal fabrication related questions while explaining antenna effect. 19. process variation in the wafer ...

1.Tell me about yourself  2.About  projects in resume (6t sram dac&its sunblocks  standard cells)  3.what are the basic layers in16nm 28nm 45nm 4.what are the constraints followed for while designing opamp ckt  5.Constraints for current mirror and differential pair 6.difference between common centroid and interdigitization patterns  7.why can't we use interdigitization  for differential pair and comm centroid for current mirror  8.why we go for matching concept  9.what are process variations  10.what is WPE and how u over come WPE 11.what is latchup&how parasitic bjt will cause short circuit path between vdd &vss 12.to flow current in bjt gate voltage is needed &how but will get gate voltage  13.can u tell me comm centroid pattern for A=3,B=3&tell me pattern using dummy and without dummy  14.what is the use of current mirror why we are using current mirror in opamp  15.difference between opamp &diff...

1) Introduce about yourself  2) Which subjects you are comfortable ? (I told digital design & Verilog , I am having basic know of analog electronics ) 3) Digital questions asked --  i)Universal gates ii) implementation of gates using  muxes d iii)difference between sequential & combination circuits iv)min change code ,setup time hold time ,how to reduce setup & hold time violation v)How clk to q delay gets affected by metastability vi)How XOR is converted to buffer & inverter vii)Difference between asyn & sync counters , latch & ff , ring oscillator , FSMs , viii)half adder & it's construction  xi)what states  1100 goes in ring & Johnson counter 4)How CMOS inverter  works , latch up  5) Miscellaneous - resistor , capacitor  in series parallel questions  No verilog & No apti questions

1) CMOS inverter characteristics ( significant of Id and Vds )  2) More questions on power dissipation in CMOS ( leakage current ) and how to reduce dynamic and static power dissipation.  3) What are the challenges in deep sub micron? 4) Written test questions discussion ( only technical ) . 5) Academic projects . 6) About synthesis ( logical and physical synthesis ) . 7) Inputs for synthesis , write any 3 .sdc  8) Source of clock , difference between generated clock and master clock . They will give you one scenario about to this .  9) Why transmission gates are not preferred in design ( very less )  10) Setup , hold , skew fixing of setup and hold timing.  11) Setup can negative ? How to fix negative setup. 12) Based on the resume they will ask tool related questions ( only flow )

1. Basic digital electronics, mostly based on timers, counters and FFs. 2. Microcontroller- ARM architecture/ 8051 3. Interrupts,  NVICs, memory organization in uC, watchdog timers, PWMs etc. 4. Basic C programming, like masking, nested loops, bitwise operations 5. Op-Amps and their usage in uC 6. ADC and DACs internal structure and working  7. Any projects you've worked on! 8. Communication protocols like CAN, IIC, SPI, UART etc. And their internal functioning! 9. Clocks - difference between PLL, FLL, and how to create clock divider circuit (both odd division and even) and how to upscale  10. Power electronics - buck, boost, LDOs and their internal working!  11. Ripple currents and use of inductors, also, decoupling capacitors 12. Difference between single ended lines and differential pairs and why we use them 13. Some basic validation procedure including PVTF flow