VIT Campus Interview 2021 -II

Set- A

1.  UVM pr jaarha tha mai bola nhi aata
2. Task vs function
3. Tell me about your
4. Asic setup & hold time
5. SV ka assertion
6. Puzzle:
7. There are three boxes, one contains only apples, one contains only oranges, and one contains both apples and oranges. The boxes have been incorrectly labeled such that no label identifies the actual contents of the box it labels. Opening just one box, and without looking in the box, you take out one piece of fruit. By  Fork join
8. What is leakage and dynamic power

Set-B

(1)Current project

(2)Setup time 

(3)Hold time

(4)Latch

(5)Reg.

(6)What is your interest 

(7)Inversion layer (MOSFET)

(8)Proportion delay

(9)insertion delay

(10)Fanout 

(11)Coupling capacitor

(12)Dynamic power

(13)Leakage current

(14)Threshold voltage

(15)Cross talk

(16)Are know about CMOS circuit (logic gate) /Synthesis/ ASIC/LVS Extraction??

Set-C

1. Steps of physical design
2.  Techniquefor reducing leakage and dynamic power
3. Need of testing
4. Difference between analog and digital
5. About project explain one full project
6.  Difference berween embeded and gpp  Asic , Explain with real time application
7. System verilog and verilog difference

Set -D

1. Tell me about yourself
2. Physical design
3. STA
4. Synthesis
5. Tool flow synopsis
6. Digital logic design
7. Gates
8. Buffer using nand gate 
9. Buffer using xor
10. Timing analysis
11. Timing constraints
12. How to write constraints file
13. Setup time 
14. Latch and ff

Set-E

1.  what is synthesis
2.  On what dynamic power depends
3.  differnce in asic and fpga
4. Introduce yourself 
5. Explain any project
6. What you like analog or digital?
7. What will happen if we connect Q output to D input of flip flop?
8. What is setup time?
9. What will happen if it violates?
10. Hardware if we multiply 16bit with 12?

Set-F

1. Tell me about yourself
2. Explain your project
3. single electron transistor
4. Xor gate low power
5. Truth table of Xor
6. How to impliment Xor at Buffer
7. asic flow(Explain Describe all parts  specially Physical design)
8. Latch flip flop
9. STA
10. setup time hold time
11. Latchup
12. Latchup Circuit 
13. Tcl,perl,python ?? 

Set-G

1. difference between always and initial block
2.  what is differnce between function and task
3.  what is setup and hold time
4.  hw to remove setup and hold violations
5. difference in mealy and moore state  machine
6. what is sensitivity list
7. difference in intra and inter delay assignment
8. what is constraints in asic synthesis
9.  what is difference in latch and flipflop

Set-H (PD role)

1. Physical design flow in brief each step
2. How you carried out physical synthesis in dc tool
3. In prime time what u observed
4. How you link your library to your design
5. What is sdc file
6. What is ur design contrents
7. Setup hold hardware perspective
8. Power optimization 
9. Hvt lvt rvt device level discussion
10. Formal verification explanation
11. Corner analysis
12. Clock tree synthesis related questions
13. Dynamic variation in design
14. Difference between flattened and structure netlist what is use of that
15. Dynamic power optimization
16. Various path in our design
17. Switching activity file use
18. Clock skew uncertainty
19. Global local skew
20. Powerplanning explanation