Arm 2021-Architecture verification engineer

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 1.Pipelining

2.Performance improvement in a pipelined processor compared to a non pipelined processor. 

3.Basics of System verilog and system verilog assertions -> Randomisation and constrained randomisation 

4)Types of cache mapping -> Direct, k-way set associative and fully associative mapping, cache tagging 

5)Need for instruction and data caches 

6)Systolic arrays

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