STM Interview -Intern Campus 2021

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1) Introduce about yourself 

2) Which subjects you are comfortable ? (I told digital design & Verilog , I am having basic know of analog electronics )

3) Digital questions asked -- 

i)Universal gates
ii) implementation of gates using  muxes d
iii)difference between sequential & combination circuits
iv)min change code ,setup time hold time ,how to reduce setup & hold time violation
v)How clk to q delay gets affected by metastability
vi)How XOR is converted to buffer & inverter
vii)Difference between asyn & sync counters , latch & ff , ring oscillator , FSMs ,
viii)half adder & it's construction 
xi)what states  1100 goes in ring & Johnson counter

4)How CMOS inverter  works , latch up 
5) Miscellaneous - resistor , capacitor  in series parallel questions 
No verilog & No apti questions

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