Intel 2021-Intern

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Set-A
 1. Can u quickly brief about your self for next 5 minutes?
2. How good u are in digital electronics?
3. Can u quickly built xnor gate with muxes?
4. How many 2:1 muxes require to built an xnor gate?
5. There is a triangle, each corner of the triangle have one object. That objects can move any direction  from the corners.What is the probability that any two objects collide each other?
6. What is SETUP and HOLD times?
7. How will u solve the SETUP violation?

Set-B
  1. Difference between asic and fpga
  2. What are Trade of parameter in lpic? Area speed and power
  3. If setup or hold violates what will be output
  4. What is synthesis.
  5. Tool used for synthesis
Set-C
1.which hdl languages do u know?
2.fibonacci series in verilog you reach a number that 16bit register cannot hold
3.a system which checks if 16bit input is a prime number and gives one bit output as 1 if it prime and 0 if it not prime
4.how approximate multipliers implemented in my project
What was my approach? What was error? How did u achieve that give me an example or piece of ur design? How accuracy and power are traded in ur design? On what basis u vary them?
5.how did u implement ur atm project? What is its complexity? What are different states in it? How state traversal take place? What type of state machine is your project? What max operating frequency of ur project?
6.aptitude question on train running opposite started at different times, different speeds, when do they reach destination? Who reaches first? When do they meet together?

Set-D
  1. Interrupt in microprocessor
  2. How much of 64KB memory are required to build 1MB memory?
  3. Full case and parallel case in verilog
  4. Explain projs
  5. Find output of a given verilog code
  6. Why bist is used,it's advantages
  7. Diff between CMOS and domino logic, compare power dissipation in the two
  8. Various power reduction techniques
  9. Basics of verilog - blocking and non blocking
  10. Complete pd flow
  11. Uvm structure. Why uvm ? 
  12. System verilog tesbench structure
  13. Flags of perl n tcl
Set-E

Some Questions based on Resume
  1. synopsys tools used
  2.  what is synthesis
  3.  what is setup and hold time
  4.  difference between always and initial block
  5.  what is differnce between function and task
  6.  what is sensitivity list
  7.  hw to remove setup and hold violations
  8.  differnce in asic and fpga difference in intra and inter delay assignment
  9.  difference in mealy and moore state  machine
  10.  what is constraints in asic synthesis
  11.  what is difference in latch and flipflop
Set-F

1. What are the different types of amplifier
2. Their gain formula
3. Why  -ve is coming in gain formula
4. Inv charac
5.how graph varies with size of tran chages
6.some qus from ptl logic
7.FSM drawing nd code for 2 different sequences
8.what is set up nd hold
9.2 sums from STA

Set-G (STA-role)
1. Can u introduce yourself? and can u brief ur technical skills, your strong areas and area of interests?
2. What are the things u aware of physical verification?
3. How can u divide ASIC flow from RTL to GDS(tapeout) into 4 or 5 steps??
4. What exactly the difference between pre-layout STA and post layout STA?
5. What is the model u use during prelayout STA and during post layout STA?
6. Why the accuracy is less in pre-layout STA and more in post layout STA ?
7.  What is the extra information u get after physical synthesis and what is the information u dont have before physical synthesis?
8. Which part of the digital logic design u are interested and why?
9. For an xyz STA tool, what are the inputs u are going to give and what are the outputs u are going to get?
10. What is the very first thing required for an STA analysis?
11. What do u mean by a synthesis code?
12. Will STA go for the false path analysis also?
13. What are the construction  part so to  analyze these setup time and a hold time, basically what are the list of elements used to get an accurate picture of SETUP and HOLD?
14. What are the factors which will influence these SETUP and HOLD time?
15. If it is true that because of Crosstalk, there is an increase in delay then it is good for HOLD time right? Then y u call crosstalk as a disadvantage?
16. What are the different types of power dissipations in a digital ckt?
17. Why static power dissipation is dominating as we go on scaling?
18. Tell me about ur project?

Set-H
1.Explain about projects
2.What is the meaning of alpha=0.4 in low power
3. Is task and function synthesiable . If yes what is the hardware architecture?
4. What is latch and flip flop
5. What is blocking and non blocking
6. Difference between Mealy and moore
7. Trade off PTA
8. ASIC flow
9. What is formal verification
10.setup and hold fix
11.aptitude questions
12. What constraints contain?
13. Why is the use of quartus prime.
14. For formal verification which tool do you use
15. What is interrupt in microprocessor?
16. How many address lines do you require?
17. Difference between combinational and sequential
18. Why latch will take less power compared to flipflop
19. If you have an AOI ckt in data path you can't decrease the delay in data path in set up. What are other aspects to decrease the delay without using buffer?
20. Difference between structural and behavioral modelling.
21. Difference between task and function.

Set-I

1. Project details 
2. Two separate always blocks a1 and a2. Some condition in a2 should stop the execution of a1. (Verilog)
3. System verilog concepts - assertions, constraints
4. Oops concepts
5. Fork join
6. Or using mux
7. What is glitch . How to remove it.
8. Make an array with all unique elements
9. Sort an array with min. No. Of comparisons.
10. Perl basics- diff btw single and double quotes
11. Diff btw latch n flipflop
12. Freeze statement in verilog
13. Automatic task

Set-J
  1.  If u r using clock gating then is thr any glitch or not
  2.  Low power tech
  3. Drive strength of input buffer is not tht much enough so if u hv n number of buffers n inveters wht and how many u will use
  4. How will apply it he gave me some situation n ask me to apply it
  5. So gradually ill start increasing inverters one by one serially
  6. Then he asked me if one buffer driving 10 another load buffer
  7.  Wht will u prefer synchronous reset or asynchronous
  8. So logical efforts ka logic lagake i said according to logical efforts ...i wud suggest ill use inverter...how many tht depends upon load capacitor
  9.  interchange 2 var. without using 3rd variable
  10. AND gate using MUX
Set-H

  1. Project briefing
  2. Subj u knw
  3. Sta basics 
  4. Setup.hold multicycle path 
  5. How to solve violation
  6. Verilog related questions 
  7. Delay always block initial
  8. Divison logic 
  9. Fork and join
  10. Stop watch timer implementation
  11. Function and task
  12. Inside function delay is possible?
  13. Physical design flow
  14. After tapout process variation detection wrt freq
  15. Ocv related questions
  16. 1 apptitude type question
  17. Latch infer eg.
  18. Cell delay
  19. Transportation delay insertion delay
  20. Mealy moore
  21. Latch flipflop
  22. Hardware perspective of hold and setup
  23. Clock gating 
  24. Crosstalk signal integraty
  25. Single clock multicycle path possible?
  26. Verification of design
  27. Lastly quntum tunneling based of tfet

Comments

  1. Gyanvi29 May 2021 at 18:22

    This is really helpful. Thanks for sharing. I just have a question, what is the significance of sets here?

    ReplyDelete
    Replies
    1. Vishnu28 September 2021 at 21:42

      There were different panels for Intel interview (Campus) so I clubed them together so that it will be easy to understand, nothing specific

      Delete

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