Juntran Interview -Analog Layout Engineer 2021

-

1.Tell me about yourself 
2.About  projects in resume (6t sram dac&its sunblocks  standard cells) 
3.what are the basic layers in16nm 28nm 45nm
4.what are the constraints followed for while designing opamp ckt 
5.Constraints for current mirror and differential pair
6.difference between common centroid and interdigitization patterns 
7.why can't we use interdigitization  for differential pair and comm centroid for current mirror 
8.why we go for matching concept 
9.what are process variations 
10.what is WPE and how u over come WPE
11.what is latchup&how parasitic bjt will cause short circuit path between vdd &vss
12.to flow current in bjt gate voltage is needed &how but will get gate voltage 
13.can u tell me comm centroid pattern for A=3,B=3&tell me pattern using dummy and without dummy 
14.what is the use of current mirror why we are using current mirror in opamp 
15.difference between opamp &differential opamp 
16.what is antenna effect what happened to mosfet because of antenna effect &how u over come antenna effect 
17.what is electromigration formula for EM 
18.what is standard cell &what are constraints followed while designing standard cells, how u calculate height of standard cells

Comments

Post a Comment

Popular posts from this blog

Qualcomm Interview (DFT Role)- Fresher

-
There were in total 5 rounds (4 technical rounds + 1 HR round) First round: 1. What do I understand by DFT and the need for DFT? 2. What are scan flip flops? 3. What are the different simulation techniques for testing? What do you infer from transient delay simulation? 4. A circuit with several and-or gates was given, need to identify the input test vector for detecting a slow-to-rise fault at a particular net. 5. What is BIST?  5b. What are the different techniques used for compaction?  6. What is boundary-scan standard? (JTAG) 7. How do you rank various sorting algorithms? (insertion, bubble, etc) 8. What do you understand from hazards in a processor design? How did you overcome control hazards? 9. What happens in a deep pipelined system? (Performance related, flushing all stages of the pipeline when branch prediction fails. Increased latency). 10. Write a Verilog code for a RAM, let the address space be a parameter. 11. Are you familiar with writing scripts in- bash, PERL, ...
Read more

AMD Interview questions - Physical Design

-
(1st round -- 45 minutes)**  1) Introduce myself.  2) Operation of MOSFET.  3)Types of MOSFET.  4) What is the difference between BJT, MOSFET and CMOS.  5) Why CMOS. 6) Why cmos for low power applications.  7) Basics questions on current equation of MOSFET.  8) basic questions on layers of MOSFET.  9) What is threshold voltage.  10) some questions on equation of threshold voltage.  11) PVT parameters.  12) what is the secondary effects.  13) Voltage divider rule.  14) series circuit operation.  15) parallel circuit operation.  16) oscillator operation.  17) universal gates.  18) Realization of XOR and XNOR using NAND and NOR gates.  19) Which has highest area NAND or NOR and Why.  \20) ASIC vs SOC. (2nd round --- 45 minutes )*   1) Introduce myself.  2) Complete PD flow.  3) inputs to the PD tool.  4) Some commands on Innovus tool.  5) what are the end cap cells w...
Read more

Cerium systems fresher recruitment Interview Questions [1hr]

-
1) What is FPGA ? 2) What is difference between ASIC and FPGA ? 3) Can we replace FPGA with ASIC ? 4) What FPGA consists of actually ? 5) Tell the flow of FPGA like how we will implement a code on FPGA ? 6) What are Universal gates?  Implemented NOR gate using Nand gate? Is Mux Universal gate ? If yes implement And & Or gates using 2:1 mux ? 7) Basic diff between Latch & FF ? 8) Make a D latch using 2:1 Mux ? 9) Implement the ckt for 101 pattern detecting don't use the FSM but implement in sequential ? 10) Draw the CMOS gate for 2-input Nand & 2-input Nor gates ? 11) What are synthesizable and unsynthesizable constructs in Verilog? which one will be used when ? 12) Write verilog code for up-down counter? 14) Why Nand gate is preferable over Nor gate ? 15) Draw 3-bit Ring and Johnson Counter along with their States ?
Read more