Juntran Interview -Analog Layout Engineer 2021

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1.Tell me about yourself 
2.About  projects in resume (6t sram dac&its sunblocks  standard cells) 
3.what are the basic layers in16nm 28nm 45nm
4.what are the constraints followed for while designing opamp ckt 
5.Constraints for current mirror and differential pair
6.difference between common centroid and interdigitization patterns 
7.why can't we use interdigitization  for differential pair and comm centroid for current mirror 
8.why we go for matching concept 
9.what are process variations 
10.what is WPE and how u over come WPE
11.what is latchup&how parasitic bjt will cause short circuit path between vdd &vss
12.to flow current in bjt gate voltage is needed &how but will get gate voltage 
13.can u tell me comm centroid pattern for A=3,B=3&tell me pattern using dummy and without dummy 
14.what is the use of current mirror why we are using current mirror in opamp 
15.difference between opamp &differential opamp 
16.what is antenna effect what happened to mosfet because of antenna effect &how u over come antenna effect 
17.what is electromigration formula for EM 
18.what is standard cell &what are constraints followed while designing standard cells, how u calculate height of standard cells

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